Analog/Mixed Signal Architect

As an Analog Architect, you will spearhead pathfinding efforts and work on early prototypes of innovative analog and mixed-signal solutions for Lighmatter’s next-generation optical-engine products. You will then work closely with the engineering team to take your ideas to high-volume production. This role requires a deep understanding of high-frequency systems-on-chip (SoCs), high-speed (100+ Gbaud) serial and electro-optic interfaces. The role also requires creativity, analytical skills, and clear communication skills. You may represent the company at technical conferences as an example of our technical leadership.

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build a new kind of computer from the ground up and to solve groundbreaking challenges along the way. Work with people who love to build and who thrive in technically diverse environments where great ideas are prioritized.

Responsibilities

• Architect high-speed (200Gbaud and beyond) electro-optical interfaces for Lightmatter’s next-generation co-packaged optics (CPO) solutions.
• Design next-generation high-speed DACs, linear drivers and TIAs in the latest FinFET process nodes.
• Actively collaborate across disciplines—with electronics, photonics, and mechanical engineering teams—to specify the requirements and solutions for circuit blocks, SoCs, debug, and validation.
• Collaborate with the product team to develop our future technological and product roadmap in the context of industry trends.
• Work closely with test and validation engineers to validate hardware against simulation prediction to ensure high performance and high yield.
• Publish and present novel ideas and participate in premier technical conferences.
  
  

Qualifications

• A Ph.D. degree in Electrical Engineering or similar discipline with at least 5+ years of experience of designing high-speed analog circuits in TSMC N3/N5/N7.
• Hands-on experience in high-speed SERDES design in advanced process nodes (7nm and below).
• Deep technical background and a proven track record of innovation in their area of expertise.
• Strong understanding of how the layout impacts the SERDES performance.
• Familiarity with analyzing the impact of package and PCB on SERDES performance.
• Familiarity with UCIe, PAM4, and other high-speed SerDes.
• Strong background with using circuit and electromagnetic simulation tools needed for high-speed mixed-signal circuit design: Cadence virtuoso, Verilog-A, EMX or equivalent tools.

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