SoC - Chiplet Design Lead

The SoC Chiplet Design Lead will drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC and automotive markets that push the boundaries of performance, scalability, and efficiency. You’ll lead cross-functional teams through the entire SoC lifecycle—from concept and architecture through RTL, verification, and tape-out—while ensuring design excellence and integration success.

This role is hybrid, based out of Toronto, Ottawa, Boston, Austin, or Santa Clara, with potential for remote work within North America on a case-by-case basis.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep background in SoC and chiplet design, with expertise in RTL design (Verilog/SystemVerilog) and digital architecture.
• Experienced in cross-functional collaboration, partnering with system, verification, physical design and packaging teams to deliver complex silicon.
• Skilled at balancing tradeoffs across performance, power, cost, and features.
• A strong technical leader and mentor, with a passion for developing high-performing engineering teams.
  
  

What We Need

• Proven experience leading end-to-end SoC development, from concept to volume production.
• Mastery of SoC verification, synthesis, and timing closure workflows.
• Ability to manage internal and third-party IP integrations, lead design reviews, and closely collaborate with the DFT team
• Strategic mindset to align technical goals with product timelines and quality targets.
  
  

What You Will Learn

• Building next-generation SoC chiplet architectures at advanced process nodes (e.g., 7nm, 5nm).
• Applying cutting-edge low-power and high-speed design (RISCV, UCIe, coherent fabrics, etc.).
• Enhancing cross-domain collaboration between hardware, software, and packaging disciplines.
• Shaping best practices and tools for scalable, efficient SoC design and validation.