Staff Digital Design Engineer

As a Staff Digital Design Engineer, you will participate in the RTL development, integration, simulation, debug, and silicon implementation of best-in-class energy-efficient processors. You will regularly work with the verification, physical design, compiler development, test and validation, and emulation teams. You will be responsible for understanding high-level specifications for Efficient’s chips, and will participate in and execute all steps of a robust IC Design flow.

Key Responsibilities

• Front-end Verilog / System Verilog design and integration. Design, document, and implement large functional blocks of design while adhering to the design requirements. Integrate IPs developed in-house and procured from external vendors
• Develop a deep understanding of Efficient’s ultra-efficient compute architecture, and make improvements to it using relevant industry experience.
• Develop and maintain unit-level test cases and debug top-level RTL and netlist simulations
• Work with the verification team to review verification plans, debug test case failures, and analyze and review coverage statistics. Assist the verification team with exclusions to meet a 100% coverage goal
• Develop module-level and top-level synthesis constraints. Run and review synthesis to check the correctness of constraints. Work with the physical design team to identify and resolve timing issues.
• Drive best practices in clock/reset-domain (CDC/RDC) verification and linting, building automated checks and reusable methodologies that raise design quality across teams
• Define and implement an energy-efficient architecture, partitioning the design into multiple power domains. Own power-domain and sequencing verification by building, automating, and maintaining checks with industry-standard tools and scripts.
• Estimate power consumption of digital circuits in specific modes and scenarios by using simulation and other industry-standard tools.
• Be a role model for junior engineers. Mentor and coach junior engineers on design concepts and on the adoption of new tools and methodologies.

Qualifications

Required:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of hands-on experience in front-end digital design and ASIC development across multiple product cycles.
• Strong understanding of RTL-to-Netlist implementation, DFT concepts, constraint development, synthesis, and static timing analysis.
• Expertise in running and debugging RTL and gate-level simulations.
• Proficiency with power-domain partitioning, UPF, and power-aware simulation/debug.
• Demonstrated experience interpreting reports from and providing waivers for CDC, RDC, and lint checks using industry-standard tools.
• Knowledge of widely used industry interfaces (e.g., I2C, SPI, I2S, UART, MIPI, HDMI, LVDS, USB, PCIe).
• Proficiency with modern development infrastructure: CI pipelines, Git/GitHub workflows, and AI-assisted design/verification tools.
• Strong familiarity with engineering productivity tools such as Jira (task/sprint tracking) and Confluence (documentation and knowledge sharing).
• Excellent teamwork skills and the ability to thrive in a fast-paced, multitasking environment.

Preferred:

Expertise in one or more of the following areas is a strong plus:

• Processor architectures
• Low-power design techniques
• Analog design and mixed-signal integration
• AMS and real-number modeling
• FPGA design
• Hardware emulation and acceleration platforms

We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.