Sr. Staff Engineer, Hardware Infrastructure Lead

We're looking for an Engineering Manager to lead our hardware infrastructure team supporting the development of leading-edge RISC-V CPUs. You'll manage a team responsible for the tools, methodologies, and compute infrastructure that enable our hardware design teams to build, verify, and debug complex CPU designs. This role requires both technical depth and strong leadership skills to buildand scale a high-performing team in a fast-paced startup environment.

This role is hybrid based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

What You’ll Do

• Lead and grow a team of infrastructure engineers supporting RISC-V CPU design and verification.
• Define strategy and roadmap for regression infrastructure, build systems, and debug tooling.
• Partner closely with hardware design leadership to understand requirements and prioritize work.
• Oversee development and maintenance of CI/CD pipelines for hardware design flows.
• Establish team processes for incident response and first-line compute support.
• Drive continuous improvement in build times, regression throughput, and infrastructure reliability.
• Balance hands-on technical involvement with team development and strategic planning.
• Recruit, mentor, and develop engineers with diverse technical backgrounds.
• Communicate infrastructure status, roadmaps, and technical tradeoffs to stakeholders.

What You Bring

• 3+ years of engineering management experience, preferably in hardware or infrastructure teams.
• Strong technical background in hardware design flows, verification, or related infrastructure.
• Experience with regression frameworks, build systems, and CI/CD methodologies.
• Understanding of compute infrastructure and HPC environments.
• Proven ability to build and scale high-performing technical teams.
• Strong collaboration and communication skills across engineering disciplines.
• Experience managing on-call rotations and support processes.
• Comfortable with ambiguity and rapid priority shifts in a startup environment.

Nice to Have

• Direct experience with RISC-V or CPU design flows.
• Background in EDA tools and verification methodologies.
• Experience with LSF or similar workload managers.
• Familiarity with commercial HPC storage solutions.
• Knowledge of containerization and automation technologies.
• Previous startup experience, especially in hardware or semiconductor companies.
• Technical depth in areas like SystemVerilog, Python, or hardware debug tools.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.